1. Field of the Invention
The present invention relates to semiconductor memory devices and, more particularly, to electrically programmable memory devices with improved programmability.
2. Description of the Related Art
Electronically programmable read only memory (EPROM), erasable electronically programmable read only memory (EEPROM) and Flash memory are classes of floating gate memory devices. More particularly, these floating gate memory devices are programmable memory devices which use floating gates as charge storage layers. Conventionally, programming of floating gate memories has been done in small programming steps wherein after the completion of each programming step a verifying operation must be performed to determine the validity of the last programming step. The verifying operation has typically been done as a separate operation. For example, such repetitive programming techniques are further described in U.S. Pat. No. 5,172,338 and U.S. Pat. No. 5,220,531. One disadvantage of these conventional repetitive programming techniques is that a long time is required for programming to complete largely because of the inefficiency of having to switch between a programming mode of operation and a verify mode of operation after each programming step. Another disadvantage of these conventional repetitive programming techniques is the need to repetitively switch between a high voltage levels used in a programming mode of operation and lower voltage levels used in a verify mode of operation.
More recently, a programming scheme for floating gate memories has been described in which the verifying operation is able to be done concurrently with the programming operation. Here, the programming is achieved over various phases. A differential pair amplifier monitors the programming operation to detect if a programming phase has been completed. More particularly, the differential pair amplifier compares a voltage on a selected bit line with a program-verify voltage produced by a bandgap derived reference generator. Upon the completion of a particular programming phase, the bandgap reference will be set to another program-verify voltage that corresponds to the next programming level. This technique is described in greater detail in U.S. Pat. No. 5,712,815, which is herein incorporated by reference. One disadvantage of this approach is that implementation of a bandgap derived reference generator requires a large amount of semiconductor die area to implement (typically, on the order of 15 gates and at least one bipolar transistors). Therefore, only a limited number of bandgap reference generators are able to be practically utilized in a semiconductor memory device. Another disadvantage of this approach is that in order to program memory cells a series of programming phases are needed. As a result, the programming and verification operations still require a significant amount of time to complete.
In the view of the foregoing, there is a need for faster and more efficient schemes for programming electrically programmable memory cells.